module esc_information_registers(
    input epu_clk,
    input rst_n,

    input pdi_epu_re,
    input [15:0] pdi_epu_addr,
    output reg [7:0] epu_pdi_dout,
    output reg epu_pdi_dout_valid,

    input ecat_epu_re,
    input [15:0] ecat_epu_addr,
    output reg [7:0] epu_ecat_dout,
    output reg epu_ecat_dout_valid
);
    wire [7:0] type_r;
    wire [7:0] revision_r;
    wire [15:0] build_r;
    wire [7:0] fmmu_support_r;
    wire [7:0] syncmanager_support_r;
    wire [7:0] ram_size_r;
    wire [7:0] port_descripter_r;
    wire [15:0] esc_features_supported_r;

    assign type_r = 8'h00;
    assign revision_r = 8'h00;
    assign build_r = 16'h0000;
    assign fmmu_support_r = 8'h08;
    assign syncmanager_support_r = 8'h08;
    assign ram_size_r = 8'h08;
    assign port_descripter_r = 8'h0f;
    assign esc_features_supported_r = 16'h0;

    always @(posedge epu_clk or negedge rst_n) begin
        if(!rst_n) begin
            epu_pdi_dout <= 0;
            epu_pdi_dout_valid <= 0;
        end
        else if(pdi_epu_re) begin
            case(pdi_epu_addr)
                16'h0000: begin
                    epu_pdi_dout <= type_r;
                    epu_pdi_dout_valid <= 1'b1;
                end
                16'h0001: begin
                    epu_pdi_dout <= revision_r;
                    epu_pdi_dout_valid <= 1'b1;
                end
                16'h0002: begin
                    epu_pdi_dout <= build_r[7:0];
                    epu_pdi_dout_valid <= 1'b1;
                end
                16'h0003: begin
                    epu_pdi_dout <= build_r[15:8];
                    epu_pdi_dout_valid <= 1'b1;
                end
                16'h0004: begin
                    epu_pdi_dout <= fmmu_support_r;
                    epu_pdi_dout_valid <= 1'b1;
                end
                16'h0005: begin
                    epu_pdi_dout <= syncmanager_support_r;
                    epu_pdi_dout_valid <= 1'b1;
                end
                16'h0006: begin
                    epu_pdi_dout <= ram_size_r;
                    epu_pdi_dout_valid <= 1'b1;
                end
                16'h0007: begin
                    epu_pdi_dout <= port_descripter_r;
                    epu_pdi_dout_valid <= 1'b1;
                end
                16'h0008: begin
                    epu_pdi_dout <= esc_features_supported_r[7:0];
                    epu_pdi_dout_valid <= 1'b1;
                end
                16'h0009: begin
                    epu_pdi_dout <= esc_features_supported_r[15:8];
                    epu_pdi_dout_valid <= 1'b1;
                end
                default: begin
                    epu_pdi_dout <= 8'h00;
                    epu_pdi_dout_valid <= 1'b0;
                end
            endcase
        end
        else begin
            epu_pdi_dout <= 8'h00;
            epu_pdi_dout_valid <= 1'b0;
        end
    end

    always @(posedge epu_clk or negedge rst_n) begin
        if(!rst_n) begin
            epu_ecat_dout <= 0;
            epu_ecat_dout_valid <= 0;
        end
        else if(ecat_epu_re) begin
            case(ecat_epu_addr)
                16'h0000: begin
                    epu_ecat_dout <= type_r;
                    epu_ecat_dout_valid <= 1'b1;
                end
                16'h0001: begin
                    epu_ecat_dout <= revision_r;
                    epu_ecat_dout_valid <= 1'b1;
                end
                16'h0002: begin
                    epu_ecat_dout <= build_r[7:0];
                    epu_ecat_dout_valid <= 1'b1;
                end
                16'h0003: begin
                    epu_ecat_dout <= build_r[15:8];
                    epu_ecat_dout_valid <= 1'b1;
                end
                16'h0004: begin
                    epu_ecat_dout <= fmmu_support_r;
                    epu_ecat_dout_valid <= 1'b1;
                end
                16'h0005: begin
                    epu_ecat_dout <= syncmanager_support_r;
                    epu_ecat_dout_valid <= 1'b1;
                end
                16'h0006: begin
                    epu_ecat_dout <= ram_size_r;
                    epu_ecat_dout_valid <= 1'b1;
                end
                16'h0007: begin
                    epu_ecat_dout <= port_descripter_r;
                    epu_ecat_dout_valid <= 1'b1;
                end
                16'h0008: begin
                    epu_ecat_dout <= esc_features_supported_r[7:0];
                    epu_ecat_dout_valid <= 1'b1;
                end
                16'h0009: begin
                    epu_ecat_dout <= esc_features_supported_r[15:8];
                    epu_ecat_dout_valid <= 1'b1;
                end
                default: begin
                    epu_ecat_dout <= 8'h00;
                    epu_ecat_dout_valid <= 1'b0;
                end
            endcase
        end
        else begin
            epu_ecat_dout <= 8'h00;
            epu_ecat_dout_valid <= 1'b0;
        end
    end
endmodule
